library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all; 
--use ieee.std_logic_signed.all;



entity calu is port(
	ris : out std_logic_vector (31 downto 0);
	z: out std_logic;
	c: out std_logic


);end entity;


architecture bcalu of calu is 

component prova  port(

	i1 : in std_logic_vector(31 downto 0);
	i2 : in std_logic_vector(31 downto 0);
	ctrl : in std_logic_vector(3 downto 0);
	ris : out std_logic_vector (31 downto 0);
	z: out std_logic;
	c: out std_logic


); end component;

signal a,b : std_logic_vector (31 downto 0);
signal check: std_logic_vector(3 downto 0);


begin


alu_test: prova port map(a,b,check,ris,z,c);


-- process to check the control
process
begin
a<="00110000000000000000000000000000" ;
wait for 10 ns;
b<="00000000000000000000000000000011";
wait for 10 ns;
check<="0000";
wait for 10 ns;
check<="0001";
wait for 10 ns;
a<="00110000000000000000000000000011";
wait for 10 ns;
check<="0010";
wait for 10 ns;
check<="0110";
wait for 10 ns;



end process;







end architecture;


